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ltc3025 1 3025fd typical application features applications description 300ma micropower vldo linear regulator the ltc ? 3025 is a micropower, vldo tm (very low drop- out) linear regulator which operates from input voltages as low as 0.9v. the device is capable of supplying 300ma of output current with a typical dropout voltage of only 45mv. a bias supply is required to run the internal reference and ldo circuitry while output current comes directly from the in supply for high ef? ciency regulation. the low 0.4v internal reference voltage allows the ltc3025 output to be programmed to much lower voltages than available in common ldos (range of 0.4v to 3.6v). the output voltage is programmed via two ultrasmall smd resistors. the ltc3025s low quiescent current makes it an ideal choice for use in battery-powered systems. for 3-cell nimh and single cell li-ion applications, the bias voltage can be supplied directly from the battery while the input can come from a high ef? ciency buck regulator, providing a high ef? ciency, low noise output. other features include high output voltage accuracy, excellent transient response, stability with ultralow esr ceramic capacitors as small as 1f, short-circuit and thermal overload protection and output current limiting. the ltc3025 is available in a tiny, low pro? le (0.75mm) 6-lead dfn (2mm 2mm) package. 1.2v output voltage from 1.5v input supply n wide input voltage range: 0.9v to 5.5v n stable with ceramic capacitors n very low dropout: 45mv at 300ma n adjustable output range: 0.4v to 3.6v n 2% voltage accuracy over temperature supply load n low noise: 80v rms (10hz to 100khz) n bias voltage range: 2.5v to 5.5v n fast transient recovery n shutdown disconnects load from v in and v bias n low operating current: i in = 4a, i bias = 50a typ n low shutdown current: i in = 1a, i bias = 0.01a typ n output current limit n thermal overload protection n available in 6-lead (2mm 2mm) dfn package n low power handheld devices n low voltage logic supplies n dsp power supplies n cellular phones n portable electronic equipment n handheld medical instruments n post regulator for switching supply noise rejection 1mhz v in supply rejection ltc3025 bias 0.1f 1.5v 1f 0.1f li-ion or 3-cell nimh in shdn out 80.6k v out = 1.2v i out 300ma 40.2k 3025 ta01 adj gnd off on 1.5v high efficiency dc/dc buck v in (v) 1.2 0 rejection (db) 5 15 20 25 50 35 1.6 2.0 2.2 3025 ta01b 10 40 45 30 1.4 1.8 2.4 2.6 bias = 3.6v v out = 1.2v i out = 100ma i out = 300ma c out = 1f c out = 10f l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and vldo and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc3025 2 3025fd pin configuration absolute maximum ratings v bias , v in to gnd ......................................... C0.3v to 6v shdn to gnd ............................................... C0.3v to 6v adj to gnd .................................................. C0.3v to 6v v out ........................................C0.3v to v in + 0.3v or 6v operating junction temperature range (note 3) .................................................. C40c to 125c storage temperature range ................... C65c to 125c output short-circuit duration .......................... inde? nite (notes 1, 2) top view 7 dc6 package 6-lead (2mm s 2mm) plastic dfn 4 5 6 3 2 1bias gnd in shdn adj out t jmax = 125c, ja = 102c/w, jc = 20c/w exposed pad (pin 7) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LTC3025EDC#pbf LTC3025EDC#trpbf lbdy 6-lead (2mm 2mm) plastic dfn C40c to 125c ltc3025idc#pbf ltc3025idc#trpbf lbdy 6-lead (2mm 2mm) plastic dfn C40c to 125c lead based finish tape and reel part marking* package description temperature range LTC3025EDC LTC3025EDC#tr lbdy 6-lead (2mm 2mm) plastic dfn C40c to 125c ltc3025idc ltc3025idc#tr lbdy 6-lead (2mm 2mm) plastic dfn C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ parameter conditions min typ max units v in operating voltage (note 4) l 0.9 5.5 v v bias operating voltage (note 4) l 2.5 5.5 v v bias undervoltage lockout l 2.2 2.5 v v in operating current i out = 10a l 410 a v bias operating current i out = 10a l 50 80 a v in shutdown current v shdn = 0v 1 5 a v bias shutdown current v shdn = 0v 0.01 1 a v adj regulation voltage (note 5) 1ma i out 300ma, 1.5v v in 5v 1ma i out 300ma, 1.5v v in 5v l 0.395 0.392 0.4 0.4 0.405 0.408 v v i adj adj input current v adj = 0.45v C50 0 50 na out load regulation (referred to adj pin) ?i out = 1ma to 300ma C0.2 mv v in line regulation (referred to adj pin) v in = 1.5v to 5v, v bias = 3.6v, v out = 1.2v, i out = 1ma 0.07 mv bias line regulation (referred to adj pin) v in = 1.5v, v bias = 2.6v to 5v, v out = 1.2v i out = 1ma l 1.7 5.5 mv the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 1.5v, v bias = 3.6v, v out = 1.2v, c out = 1f, c in = 0.1f, c bias = 0.1f (all capacitors ceramic) unless otherwise noted. (note 3) electrical characteristics
ltc3025 3 3025fd electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 3: the ltc3025 regulator is tested and speci? ed under pulse load conditions such that t j t a . the ltc3025 is 100% production tested at 25c. performance at C40c and 125c is assured by design, characterization and correlation with statistical process control. the ltc3025i is guaranteed to meet performance speci? cations over the full C40c and 125c operating junction temperature range. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 1.5v, v bias = 3.6v, v out = 1.2v, c out = 1f, c in = 0.1f, c bias = 0.1f (all capacitors ceramic) unless otherwise noted. (note 3) parameter conditions min typ max units v in to v out dropout voltage (notes 4, 6, 7) v bias = 2.8v, v in = 1.5v, v adj = 0.37v, i out = 300ma l 45 100 mv v bias to v out dropout voltage (note 4) l 1.4 v i out continuous output current l 300 ma i out current limit v adj = 0v 680 ma e n output voltage noise f = 10hz to 100khz, i out = 300ma 80 v rms v ih shdn input high voltage l 0.9 v v il shdn input low voltage l 0.3 v i ih shdn input high current shdn = 1.2v C1 1 a i l shdn input low current shdn = 0v C1 1 a note 4: for the ltc3025, a regulated output voltage will only be available when the minimum in and bias operating voltages as well as the in to out and bias to out dropout voltages are all satis? ed. note 5: operating conditions are limited by maximum junction temperature. the regulated output voltage speci? cation will not apply for all possible combinations of input voltage and output current. when operating at maximum input voltage, the output current range must be limited. when operating at maximum output current, the input voltage range must be limited. note 6: dropout voltage is minimum input to output voltage differential needed to maintain regulation at a speci? ed output current. in dropout, the output voltage will be equal to v in C v dropout . note 7: the dfn output fet on-resistance in dropout is guaranteed by correlation to wafer level measurements. typical performance characteristics dropout voltage vs i out operating bias current vs output load bias no load operating current i out (ma) 0 70 60 50 40 30 20 10 0 150 250 3025 g01 50 100 200 300 dropout voltage (mv) t a = C40c t a = 125c t a = 25c v bias = 2.8v i out (ma) 0.01 i bias (a) 150 200 250 10 1000 3025 g02 100 50 0 0.1 1 100 300 350 400 C40c 25c 125c v bias (v) 2.5 i bias (a) 30 40 4 5 3025 g03 20 10 0 3 3.5 4.5 60 50 70 80 5.5 v in = 1.5v v out = 1.2v 125c 25c C40c
ltc3025 4 3025fd frequency (hz) 100 50 60 70 1m 3025 g10 40 30 1k 10k 100k 10m 20 10 0 rejection (db) v bias = 3.6v v in = 1.5v v out = 1.2v i out = 100ma c out = 10f c out = 1f frequency (hz) 100 50 60 70 1m 3025 g11 40 30 1k 10k 100k 10m 20 10 0 rejection (db) v bias = 3.6v v in = 1.5v v out = 1.2v i out = 100ma c out = 10f c out = 1f v in (v) 0 current limit (ma) 600 800 1000 3 5 3025 g08 400 200 0 12 4 1200 1400 1600 6 v bias = 3.6v v out = 0v typical performance characteristics v in no load operating current v in shutdown current adjust voltage vs temperature shdn threshold vs temperature current limit vs v in voltage burst mode dc/dc buck ripple rejection v in ripple rejection vs frequency bias ripple rejection vs frequency v in (v) 0.5 10 125c 85c 25c C40c 12 14 4.5 3025 g04 8 6 1.5 2.5 3.5 5.5 4 2 0 i in (a) v bias = 5v v out = 0.8v v in (v) 0.5 5 25c C40c 6 7 4.5 3025 g05 4 3 1.5 2.5 3.5 5.5 2 1 0 i in (a) 85c v bias = 5v temperature (c) C50 395 adjust voltage (mv) 396 398 399 400 405 402 0 50 75 3025 g06 397 403 404 401 C25 25 100 125 v bias = 3.6v v in = 1.5v i out = 10a temperature (c) C50 0 shdn threshold (mv) 100 300 400 500 1000 700 0 50 75 3025 g07 200 800 900 600 C25 25 100 125 v bias = 2.5v v bias = 5v v in ac 100mv/div v out ac 10mv/div v in = 1.8v v out = 1.5v c out = 1f i out = 50ma 10s/div 3025 g09
ltc3025 5 3025fd v in (v) 1.2 0 rejection (db) 5 15 20 25 50 35 1.6 2.0 2.2 3025 g12 10 40 45 30 1.4 1.8 2.4 2.6 v bias = 3.6v v out = 1.2v i out = 100ma i out = 300ma c out = 1f c out = 10f 250ma 10ma i out v out ac 10mv/div v in = 1.5v v out = 1.2v v bias = 3.6v c out = 1f 100s/div 3025 g13 typical performance characteristics 3mhz v in supply rejection transient response pin functions bias (pin 1): bias input voltage. bias provides internal power for ltc3025 circuitry. the bias pin should be lo- cally bypassed to ground if the ltc3025 is more than a few inches away from another source of bulk capacitance. in general, the output impedance of a battery rises with frequency, so it is usually advisable to include an input bypass capacitor in battery-powered circuits. a capacitor in the range of 0.01f to 0.1f is usually suf? cient. gnd (pin 2): ground. connect to a ground plane. in (pin 3): input supply voltage. the output load current is supplied directly from in. the in pin should be locally bypassed to ground if the ltc3025 is more than a few inches away from another source of bulk capacitance. in general, the output impedance of a battery rises with frequency, so it is usually advisable to include an input bypass capacitor when supplying in from a battery. a capacitor in the range of 0.1f to 1f is usually suf? cient. out (pin 4): regulated output voltage. the out pin supplies power to the load. a minimum ceramic output capacitor of at least 1f is required to ensure stability. larger output capacitors may be required for applications with large transient loads to limit peak voltage transients. see the applications information section for more informa- tion on output capacitance. adj (pin 5): adjust input. this is the input to the error ampli? er. the adj pin reference voltage is 0.4v referenced to ground. the output voltage range is 0.4v to 3.6v and is typically set by connecting adj to a resistor divider from out to gnd. see figure 2. shdn (pin 6): shutdown input, active low. this pin is used to put the ltc3025 into shutdown. the shdn pin current is typically less than 10na. the shdn pin cannot be left ? oating and must be tied to a valid logic level (such as bias) if not used. gnd (exposed pad pin 7): ground and heat sink. must be soldered to pcb ground plane or large pad for optimal thermal performance.
ltc3025 6 3025fd block diagram 3 1 6 2 4 5 in out 6a 3025 bd adj gnd shdn bias reference shdn 0.4v soft-start C + operation (refer to block diagram) the ltc3025 is a micropower, vldo (very low dropout) linear regulator which operates from input voltages as low as 0.9v. the device provides a high accuracy output that is capable of supplying 300ma of output current with a typical dropout voltage of only 45mv. a single ceramic capacitor as small as 1f is all that is required for output bypassing. a low reference voltage allows the ltc3025 output to be programmed to much lower voltages than available in common ldos (range of 0.4v to 3. 6v). as shown in the block diagram, the bias input supplies the internal reference and ldo circuitry while all output current comes directly from the in input for high ef? ciency regulation. the low quiescent supply currents i in = 4a, i bias = 50a drop to i in = 1a, i bias = 0.01a typical in shutdown making the ltc3025 an ideal choice for use in battery-powered systems. the device includes current limit and thermal overload protection. the fast transient response of the follower output stage overcomes the traditional tradeoff between dropout voltage, quiescent current and load transient response inherent in most ldo regulator architectures. the ltc3025 also includes overshoot detection circuitry which brings the output back into regulation when going from heavy to light output loads (see figure 1). applications information 300ma 0ma i out v out ac 20mv/div v in = 1.5v v out = 1.2v v bias = 3.6v c out = 1f 100s/div 3025 f01 figure 1. ltc3025 transient response adjustable output voltage the output voltage is set by the ratio of two external resis- tors as shown in figure 2. the device servos the output to maintain the adj pin voltage at 0.4v (referenced to ground). thus the current in r1 is equal to 0.4v/r1. for good transient response, stability, and accuracy, the current in r1 should be at least 8a, thus the value of r1 should be no greater than 50k. the current in r2 is the current in r1 plus the adj pin bias current. since the adj pin bias current is typically <10na, it can be ignored in the output voltage calculation. the output voltage can be calculated
ltc3025 7 3025fd using the formula in figure 2. note that in shutdown the output is turned off and the divider current will be zero once c out is discharged. the ltc3025 operates at a relatively high gain of C0.7v/ ma referred to the adj input. thus a load current change of 1ma to 300ma produces a C0.2mv drop at the adj input. to calculate the change referred to the output sim- ply multiply by the gain of the feedback network (i. e. ,1 + r2/r1). for example, to program the output for 1.2v choose r2/r1 = 2. in this example, an output current change of 1ma to 300ma produces C0.2mv ? (1 + 2) = 0.6mv drop at the output. because the adj pin is relatively high impedance (depend- ing on the resistor divider used) , stray capacitance at this pin should be minimized (<10pf) to prevent phase shift in the error ampli? er loop. additionally, special attention should be given to any stray capacitances that can couple external signals onto the adj pin producing undesirable output ripple. for optimum performance connect the adj pin to r1 and r2 with a short pcb trace and minimize all other stray capacitance to the adj pin. () out r1 r2 3025 f02 c out r2 r1 v out = 0.4v 1 adj gnd figure 2. programming the ltc3025 applications information output capacitance and transient response the ltc3025 is designed to be stable with a wide range of ceramic output capacitors. the esr of the output capaci- tor affects stability, most notably with small capacitors. a minimum output capacitor of 1f with an esr of 0.05 or less is recommended to ensure stability. the ltc3025 is a micropower device and output transient response will be a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. note that bypass capacitors used to decouple individual components powered by the ltc3025 will increase the effective output capacitor value. high esr tantalum and electrolytic capacitors may be used, but a low esr ceramic capacitor must be in parallel at the output. there is no minimum esr or maximum capacitor size requirements. extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common di- electrics used are z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but exhibit large voltage and tem- perature coef? cients as shown in figures 3 and 4. when used with a 2v regulator, a 1f y5v capacitor can lose as much as 75% of its initial capacitance over the operating dc bias voltage (v) change in value (%) 3025 f03 20 0 C20 C40 C60 C80 C100 0 4 8 10 26 x5r y5v both capacitors are 1f, 10v, 0603 case size figure 3. ceramic capacitor dc bias characteristics temperature (c) C50 C100 change in value (%) C80 C60 C40 C20 x5r y5v 20 C25 02550 3025 f04 75 0 both capacitors are 1f, 10v, 0603 case size figure 4. ceramic capacitor temperature characteristics
ltc3025 8 3025fd temperature range. the x5r and x7r dielectrics result in more stable characteristics and are usually more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. in all cases, the output capacitance should never drop below 0.4f, or instability or degraded performance may occur. thermal considerations the power handling capability of the device will be limited by the maximum rated junction temperature (125c). the power dissipated by the device will be the output current multiplied by the input/output voltage differential: (i out ) (v in C v out ) note that the bias current is less than 300a even under heavy loads, so its power consumption can be ignored for thermal calculations. the ltc3025 has internal thermal limiting designed to protect the device during momentary overload conditions. for continuous normal conditions, the maximum junction temperature rating of 125c must not be exceeded. it is important to give careful consideration to all sources of thermal resistance from junction to ambient. additional heat sources mounted nearby must also be considered. for surface mount devices, heat sinking is accomplished by using the heat-spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through holes can also be used to spread the heat gener- ated by power devices. the ltc3025 2mm 2mm dfn package is speci? ed as hav- ing a junction-to-ambient thermal resistance of 102c/w, which assumes a minimal heat spreading copper plane. the actual thermal resistance can be reduced substantially by connecting the package directly to a good heat spreading ground plane. when soldered to 2500mm 2 double-sided 1 oz. copper plane, the actual junction-to-ambient thermal resistance can be less than 60c/w. calculating junction temperature example: given an output voltage of 1.2v, an input voltage of 1.8v to 3v, an output current range of 0ma to 100ma and a maximum ambient temperature of 50c, what will the maximum junction temperature be? the power dissipated by the device will be equal to: i out(max) (v in(max) C v out ) where: i out(max) = 100ma v in(max) = 3v so: p = 100ma(3v C 1.2v) = 0.18w even under worst-case conditions, the ltc3025s bias pin power dissipation is only about 1mw, thus can be ignored. assuming a junction-to-ambient thermal resistance of 102c/w, the junction temperature rise above ambient will be approximately equal to: 0.18w(102c/w) = 18.4c the maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: t = 50c + 18.4c = 68.4c short-circuit/thermal protection the ltc3025 has built-in short-circuit current limiting as well as overtemperature protection. during short-circuit conditions, internal circuitry automatically limits the output current to approximately 600ma. at higher temperatures, or in cases where internal power dissipation causes excessive self heating on chip, the thermal shutdown circuitry will shut down the ldo when the junction temperature exceeds approximately 150c. it will re enable the ldo once the junction temperature drops back to approximately 140c. applications information
ltc3025 9 3025fd applications information the ltc3025 will cycle in and out of thermal shutdown without latch-up or damage until the overstress condition is removed. long term overstress (t j > 125c) should be avoided as it can degrade the performance or shorten the life of the part. soft-start operation the ltc3025 includes a soft-start feature to prevent excessive current ? ow during start-up. when the ldo is enabled, the soft-start circuitry gradually increases the ldo reference voltage from 0v to 0.4v over a period of about 600s. there is a short 700s delay from the time the part is enabled until the ldo output starts to rise. figure 5 shows the start-up and shutdown output waveform. v out start-up and supply sequencing during power-up, the output shutdown circuitry is not active below v in of about 0.65v dc (typical). as a result, the output voltage can drift up during power-up due to leakage current (<1 ma typical) from v in to v out . at 0.9v input, the shutdown circuitry is active and the output is actively held off. this usually causes no circuit problems and is similar to 3-terminal regulators such as the lt3080, lt1086 and lt317 which have no ground pin and can have the output rise under some conditions. a slowly rising v in with the part enabled may result in non-monotonic ramping of v out due to ldo circuitry becoming active at v in of about 0.65v (typical) as well. with fast rising inputs (>1v/ms) or with suf? cient resis- tive load on v out , output voltage rise during power-up is reduced or eliminated. such conditions also reduce or eliminate non-monotonic initial power-up with the part enabled. if v bias is sequenced up before v in , the leakage current from v in to v out may increase until the shutdown circuitry is active at a v in of about 0.65v typical. thus, to minimize v out rise during start-up, sequence up v in before v bias . at v in = 0.9v, the output is actively held off in shutdown or it is actively held on when enabled under all conditions. off 1.2v 0v on shdn v out 200mv/div t a = 25c v in = 1.5v v bias = 3.6v c out = 1f r load = 4 500s/div 3025 f05 figure 5. output start-up and shutdown
ltc3025 10 3025fd package description dc package 6-lead plastic dfn (2mm 2mm) (reference ltc dwg # 05-08-1703 rev b) 2.00 p0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (wccd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 0.56 p 0.05 (2 sides) 0.75 p0.05 r = 0.125 typ r = 0.05 typ 1.37 p0.05 (2 sides) 1 3 64 pin 1 bar top mark (see note 6) 0.200 ref 0.00 C 0.05 (dc6) dfn rev b 1309 0.25 p 0.05 0.50 bsc 0.25 p 0.05 1.42 p0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 p0.05 (2 sides) 1.15 p0.05 0.70 p0.05 2.55 p0.05 package outline 0.50 bsc pin 1 notch r = 0.20 or 0.25 s 45o chamfer
ltc3025 11 3025fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number c 07/10 added (note 3) notation to the l denotes statement in electrical characteristics section updated pin 7 in pin functions added v out start-up and supply sequencing section updated related parts section 2, 3 6 9 12 d 01/11 updated graph g11 4 (revision history begins at rev c)
ltc3025 12 3025fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2004 lt 0111 rev d ? printed in usa related parts part number description comments lt ? 1761 100ma, low noise micropower, ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 20a, i sd < 1a, v out = adj, 1.5v, 1.8v, 2v, 2.5v, 2.8v, 3v, 3.3v, 5v, thinsot tm package. low noise < 20v rmsp-p , stable with 1f ceramic capacitors lt1762 150ma, low noise micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 25a, i sd < 1a, v out = adj, 2.5v, 3v, 3.3v, 5v, ms8 package. low noise < 20v rmsp-p ltc1844 150ma, very low dropout ldo v in : 1.6v to 6.5v, v out(min) = 1.25v, v do = 0.08v, i q = 40a, i sd < 1a, v out = adj, 1.5v, 1.8v, 2.5v, 2.8v, 3.3v, thinsot package. low noise < 30v rmsp-p , stable with 1f ceramic capacitors lt1962 300ma, low noise micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.27v, i q = 30a, i sd < 1a, v out = 1.5, 1.8v, 2.5v, 3v, 3.3v, 5v, ms8 package. low noise < 20v rmsp-p lt1964 200ma, low noise micropower, negative ldo v in : C0.9v to C20v, v out(min) = C1.21v, v do = 0.34v, i q = 30a, i sd < 3a, v out = adj, C5v, thinsot package. low noise < 30v rmsp-p , stable with ceramic capacitors lt3020 100ma, low voltage, vldo v in : 0.9v to 10v, v out(min) = 0.20v, v do = 0.15v, i q = 120a, i sd < 3a, v out = adj, dfn, ms8 package output current (ma) efficiency (%) 100 90 80 70 60 50 40 0.1 10 100 1000 3025 ta03 1 v out = 1.5v v out = 1.2v typical application high ef? ciency 1.5v step-down converter with ef? cient 1.2v vldo output ltc3025 bias 0.1f 1f in shdn out 80.6k v out = 1.2v i out 300ma 40.2k 3025 ta02 adj gnd 1 3 6 4 5 2 off on off on v in c in ** 4.7f cer v in 2.7v to 5.5v * ** ? ltc3406-1.5 run 2.2h* mura ta lqh32cn2r2m33 taiyo yuden jmk212bj475mg taiyo yuden jmk316bj106ml sw 4 1 3 5 c out + 10f cer v out 1.5v 600ma v out gnd ef? ciency vs output current

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